The Asynchronous Transfer Mode (ATM) packet-switching technique is becoming the standard for switched broadband ISDN (BISDN) applications. Of the various ATM switch architectures that have been proposed, the shared-buffer-memory-based architecture appears most promising. In this architecture, incoming ATM cells (the packets) destined for different output ports are buffered on queues that correspond to those ports and that share a common memory. The cells are later retrieved from the queues for transmission on their destination ports, a cell at each port at a time.
To implement the queues, it is not practical to use a buffer memory of unlimited size, and hence the possibility of memory overflow must be taken into consideration in the design of the ATM switch. A most efficient approach to handling overflow is disclosed in published international patent application WO 91/04624. This approach initially allows the output port queues to completely consume the buffer memory. Thereafter, when an additional incoming ATM cell is received for which there is no room in the buffer memory, the lengths of the output port queues are compared to determine which is the longest. An ATM cell is discarded from the head of the longest queue, and the vacated memory space is allocated to the just-incoming ATM cell.
The ATM standard allows for different ATM cells to have different priorities. The abovementioned international patent application does not take multiple priorities into consideration. However, others do. For example, H. Kuwahara et al., "A Shared Buffer Memory Switch for an ATM Exchange", IEEE International Conference on Communications, Vol.1 Jun. 11-14, 1989), pp. 4.41-4.4.5, teach that, in a multiple-priority environment, each output port of the ATM switch has associated therewith not one, but a plurality of queues, each for buffering ATM cells of a different priority that are destined for that output port. They propose to deal with the possibility of buffer-memory overflow by allowing each queue to reach only a predetermined maximum size and thereafter discarding any additional incoming ATM cells destined for storage on any queues that have reached that maximum size. Unfortunately, this approach may result in ATM cells being discarded even while empty storage space exists in the buffer memory. It therefore lacks the efficiency of the approach described in the abovementioned international application.